Read only memory (ROM) arrays are semiconductor memory chip arrays with data permanently stored in the array. ROM arrays are made up of a plurality of ROM cells, each ROM cell includes a single transistor in an “on” or “off” state. Whether the transistor is in an “on” or “off” state depends on the inclusion of contact vias connecting an active region (e.g., source/drain region) of the transistor to VSS.
Fin field-effect transistors (FinFET) are often used in ROM cells due to better drive current characteristics and sub-threshold leakage/matching performance compared to traditional transistors. In a finFET, a gate is formed to wrap around a vertical fin structure in the vertical direction. A finFET gate electrode does not have a uniform thickness. For example, a portion of the gate electrode directly over a fin will be less thick than other portions of the gate electrode because the gate is configured to wrap around the fin. Furthermore, a planarization, e.g., chemical mechanical polish (CMP), is generally performed to remove excess gate electrode material. As a result of the planarization, the thickness of the gate electrode may vary depending on the length of the gate (e.g., thickness variation may increase as length increases).
In a ROM array, a single gate structure is typically shared by all the ROM cells in a roll. Therefore, a large ROM array (e.g., 256 cells long) may have longer gates than smaller ROM arrays (e.g., 64 cells long). Furthermore, a ROM chip may include several different ROM arrays of varying sizes. Therefore, the gates electrodes of these different ROM arrays may have varying thicknesses. Variation in gate electrode thickness may create different voltage/current characteristics (e.g., Vt/Ion) in differently sized ROM arrays of a chip, negatively affecting ROM chip performance.